1. Technical Field
Various embodiments of the present invention relate to a nonvolatile memory apparatus and, more particularly, to a nonvolatile memory apparatus with changeable operation speed and related is signal control methods.
2. Related Art
A flash memory apparatus is an example of a nonvolatile memory apparatus. In general, flash memory apparatuses are not separately developed for their intended use. Instead, the same flash memory apparatuses are used for a variety of applications. For example, unlike DRAMs, which are differently manufactured according to their applications (e.g., a mobile application, a graphic application, a main memory application, etc.), flash memory apparatuses use the same structure to apply to various applications. Accordingly, it is desirable for a flash memory apparatus to maintain not only a high speed operation protocol but also a low speed operation protocol.
FIG. 1 is a flow chart explaining a conventional method for operating a low speed flash memory apparatus. As power is applied to a flash memory apparatus (S101), the flash memory apparatus is set to a default mode (e.g., an asynchronous mode S103). Then, operations under the asynchronous mode, for example, reading, programming, and erasing, are performed (S105). Such a flash memory apparatus operating at a low speed includes a controller for controlling the entire operations and a flash memory module serving as a data storage region.
FIG. 2 is a diagram illustrating a conventional protocol for a low speed flash memory apparatus. As shown in FIG. 2, signals transmitted and received between a controller 110 and a flash memory module 120 may include a write enable signal /WE, an address latch enable signal ALE, a command latch enable signal CLE, a read enable signal /RE, input/output data IO<0:N>, a state checking signal /RB, a chip enable signal /CE, and a write protect signal /WP. The protocol of FIG. 2 is appropriate for a low speed operation. For a high speed operation, signals for synchronizing signals between a controller and a flash memory module are needed.
FIG. 3 is a diagram illustrating a conventional protocol for a flash memory apparatus that can change its operation speed. Referring to FIG. 3, a clock signal CLK and a data strobe signal DQS are introduced to apply the same flash memory apparatus to not only a low speed application but also a high speed application. In such a flash memory apparatus, when entering a synchronous mode (i.e., a synchronous mode), a pin for transmitting a write enable signal /WE is set as a pin for transmitting clock signal CLK, and a pin for transmitting a read enable signal /RE is set as a pin for transmitting a write signal /WR. Signals between a controller 210 and a flash memory module 220 are synchronized using clock signal CLK, and input/output data are strobed using data strobe signal DQS. In this way, the flash memory apparatus operates under a high speed mode.
The terms “synchronous mode” and “asynchronous mode,” as used herein, refer to, for example, a high speed operation mode and a low speed operation mode, respectively.
In a flash memory apparatus, conversion between a synchronous mode and an asynchronous mode is accomplished by a set feature command. The term “set feature,” as used herein, may refer to a command used to change an internal operation of a flash memory apparatus according to a user's desire. The asynchronous mode is the default mode, and if the set feature for conversion into the synchronous mode is inputted, the flash memory apparatus is converted into the synchronous mode. To convert into the synchronous mode, the pin used for transmission of write enable signal /WE in an asynchronous mode is converted into the pin for clock signal CLK, and the pin used for transmission of read enable signal /RE is converted into the pin for the write signal /WR. Moreover, a pin for transmitting data strobe signal DQS is enabled.
As such, while clock signal CLK and data strobe signal DQS are selectively used to support both the asynchronous mode and the synchronous mode, a further speed increase required by an application may narrow the data eye and, as a result, may result in an increased signal noise that may cause a failure.
In order to minimize the influences of narrowness of the data eye and the signal noise, complementary signals are needed. While the complementary signals play an important role of suppressing a noise effect of a signal, they may increase current consumption by twice or more when used. Accordingly, the set feature is established such that the complementary signals are used not in the asynchronous mode but in the synchronous mode.
FIG. 4 is a diagram illustrating a conventional protocol for another flash memory apparatus whose operation speed is changeable and where complementary signals are added. Referring to FIG. 4, a complementary clock signal /CLK and a complementary data strobe signal /DQS are added as complementary of signals transmitted and received between a controller 310 and a flash memory module 320.
After the flash memory apparatus is converted into a synchronous mode, if a set feature for enabling the complementary signals is inputted, buffers for inputting/outputting the complementary clock signal /CLK and the complementary data strobe signal /DQS are enabled so that a noise effect may be reduced by the complementary signals.
Conversion from the synchronous mode to an asynchronous mode is accomplished by a set feature for enabling conversion into an asynchronous mode. Since it is efficient not to use the complementary signals in the asynchronous mode, a set feature for disabling the complementary signals is separately inputted. Thus, in a currently-used flash memory apparatus, the complementary signals are continuously maintained in an enabled state even after the flash memory apparatus is converted from the synchronous mode into the asynchronous mode, and a separate set feature should be used to disable the complementary signals.
Consequently, the complementary signals are maintained in the enabled state until the set feature for disabling the complementary signals is inputted. Therefore, operation current consumption of the flash memory apparatus increases.